The present disclosure relates generally to electroluminescence (EL) display devices, and more particularly to the design of the voltage power lines used for the display elements of the electro-optical display devices and the like.
Typical electroluminescence (EL) display devices comprise of a plurality of light emitting diode (LED) elements (pixels) which are connected and arranged in a matrix, row-column array construction. Using organic light emitting diode (OLED) pixels as an example, each pixel is equipped with a switching and a driving circuit, usually comprised of capacitors and thin film transistors (TFTs) connected to scan, data and voltage power lines. The combination of these circuits and lines serve to provide display information and emission for each OLED pixel. Image display information is sent to the matrix of OLED pixels via routings of the scan and data lines that are connected to drive each OLED pixel-circuit set. Power lines provide the positive (Vdd) and negative (Vss) voltages required to power the emission of the driven EL diodes. Specifically, the Vdd power supply is connected to the driving anodes of the OLED elements and the Vss power supply is connected to the elements' cathodes.
The three line types, scan, data and power, are comprised of conducting metal alloys. Conducting metal alloys featuring low resistivity material property are used as the lines to help maintain low operating resistance minimizing the voltage drop effects due to the material properties of the lines. Resistance may be defined by the following resistance equation for a solid rod or line material, R=ρ*L/A. The equation utilizes the resistivity constant ρ for the given material, L the length of the rod or line material, and A the cross-sectional area of the rod or line material. The relationship of resistance to voltage is described by Ohm's Law, V=R*I where the voltage (V) drop across a given material for a passing current (I) is dependant upon the electrical resistance (R) of the conducting material. The construction of the display device's matrix array unfortunately results with metal line routings of different lengths and cross-sectional areas to each OLED pixel-circuit set from the originating scan, data, and or power sources. The varying routing lengths of the metal lines effectively impose varying in-line resistance values onto the various OLED pixel-circuit sets. As result, the delivered voltage level to the OLED pixels and their associated circuits may not be the same for all OLED pixel locations of the EL display device's matrix array.
FIGS. 1a and 1b are top views of two typical OLED display devices illustrating the distribution and routings of the Vdd and Vss power supply lines throughout the OLED display device. These OLED display devices are of the bottom-emitting type, where the OLED emit in the direction originating from the EL material layer, through the OLED display elements' Vdd anode material and the device substrate.
FIG. 1a shows the OLED display device 100 comprising of a device substrate 102 and an active OLED pixel display area 104. The two major power bus lines for supplying power to the OLED EL elements are shown as the Vdd bus line 106 and the Vss bus line 108, located adjacent to the active OLED pixel area 104. As viewed by FIGS. 1a and 1b, the Vss bus line 108 connections to the EL display elements of the active OLED pixel area 104 are accomplished with line routings (not shown) from the Vss bus line 108, underneath the active OLED pixel display area 104, to the OLED EL display elements. Connections from the Vdd bus line 106 to the OLED display elements of the active OLED pixel display area 104 are routed through the smaller Vdd lines 110 of FIGS. 1a and 1b. Note that the routing across the active OLED pixel area 104 for FIG. 1a is in a row alignment/arrangement, while the Vdd lines 110 of FIG. 1B is shown in a column alignment/arrangement. Each Vdd line 110 layout provides a path from their main Vdd bus line 106 to the individual OLED pixel display elements of the active OLED pixel area 104. It is also noted that the lengths of the Vdd and Vss power supply lines to each EL element location within the active OLED pixel area 104 are not equal. In other words, the total metal volume used for delivering power to each EL element location through the various metal buses and lines are not equal. This inequality of conductance paths leads to varying resistances applied to the power line routings such that varying voltages are delivered to the individual EL display elements. Further, due to the voltage drop along the line, the pixels of the display device at the far end of the supply lines 110 away from the power supply bus line 106 suffers from a relatively lower power supply level, thereby degrading the display quality.
FIG. 2 illustrates a basic cross-sectional view of an OLED device 200 within the active OLED pixel area. The device substrate 202 is shown at the bottom, with the OLED anode 204 located on the device substrate. The OLED emissive EL element 206 is shown attached to the anode 204. The cathode 208 is also attached to the OLED emissive EL element 206 on the side opposite than that of the attached anode 204. It is noted that there are other dielectric material layers and structures that may be present and located between adjacent anode 204 and cathode 208, and between certain areas of the OLED EL emissive element 206 and the adjacent metal layers, for the purpose of insulating the conducting lines and certain circuit component features from each other. These dielectric layers and structures are not shown on the FIGS. 1a, 1b and 2, to help simplify and emphasize the inventions disclosed.
Referring back to FIGS. 1a and 1b, the metal power supply bus lines, Vss lines 108 and Vdd lines 106 and 110 feature routing layouts that are two-dimensional, with no like lines in any vertically overlapping or multi-layered arrangement. The cross-sectional view of FIG. 2 also shows the non-overlapping arrangement. The cathode 208 is shown to have at least one vertical step, from one height to another within it's routing, but it is noted that the routing with the vertical step does not feature any overlap or multi-layering arrangement of the metal line.
Advanced EL display devices feature high performance image display qualities taking into consideration of factors such as brightness, contrast, resolution, colors, flicker, distortion and linearity. In addition, advanced EL display devices may feature high operational refresh speeds, as well as low overall power consumption. Varying and unbalanced levels of voltage between the OLED pixel locations of such advanced EL display devices may counteract and cause undesired effects upon the image display qualities, as well as to the operational speeds and power consumption. While efforts have been made to utilize metal lines featuring low resistivity material, more focus is needed upon the other contributing factors (e.g., length L and cross-sectional area A) to lower the resistance (R) of the metal lines.
What is desirable is an improved method for the design and routing of power supply lines that features lower resistance throughout the different routings and lengths to the individual OLED pixel emission locations since lower resistance metal lines would provide lower magnitudes of voltage drops to the OLED pixel emission elements.